1. Field of the Invention
The present invention relates in general to the fabrication of deep submicron Si MOSFETs with T-shaped gate electrode, and more particularly to the gate-oxide-damage-free fabrication of deep submicron Si MOSFETs with T-shaped gate electrode.
2. Description of the Related Art
At present, a great number of semiconductor components are fabricated using MOSFET technology. Because of the need for high level integration, the dimensions of each IC device on the wafer shrink tremendously. When the dimensions shrink to deep submicron range, the parasitic resistance of gate electrode increases significantly due to the shortening of channel length. The parasitic resistance of gate electrode in conjunction with the parasitic capacitance of the related circuits thereby leads to a degradation of speed response of the devices. Consequently, a low parasitic resistance of gate electrode becomes essential in ULSI (Ultra Large Scale Integration) manufacturing. There are some approaches to achieve a gate of low parasitic resistance, and one of them is a well-known T-shaped gate design.
The following illustrates a T-shaped gate process of the prior art for deep submicron Si MOSFET's fabrication.
(1) A gate oxide layer 12 having a thickness of about 4 nm is first thermally grown on a P-type Si substrate 11, as shown in FIG. 1A. PA0 (2) Thereafter, an in situ P-doped 1st polysilicon layer 13 of about 200 nm in thickness is deposited on the gate oxide layer 12. PA0 (3) Subsequently, a photolithographic process and a RIE (Reactive Ion Etching) plasma treatment are utilized to shape the 1st polysilicon layer 13 into a conventional gate electrode pattern, as shown in FIG. 1A. PA0 (4) Next, using a LPCVD (Low Pressure Chemical Vapor Deposition) technique, a TEOS (Tetra-Ethyl-Ortho-Silicate)-oxide layer 14 having thickness of about 550 nm, which is thicker than the 1st polysilicon layer 13, is deposited on the top surface of the wafer, as shown in FIG. 1B. PA0 (5) In a process shown in FIG. 1C, the top surface of the TEOS-oxide layer 14 is planarized by a CMP (Chemical Mechanical Polishing) technique. PA0 (6) In a process shown in FIG. 1D, a BOE (Buffer Oxide Etch) etching step is utilized to remove part of the TEOS-oxide layer 14, and the remaining thickness of the TEOS-oxide layer 14 is kept about 100 nm. Therefore, the top of the 1st polysilicon layer 13 is exposed. PA0 (7) In a process shown in FIG. 1E, a 2nd polysilicon layer 15 having thickness of about 200 nm is deposited on the top surface of the wafer. PA0 (8) Thereafter, the as-deposited 2nd polysilicon layer 15 is being etched back to the top surface of the TEOS-oxide layer 14, and the remaining part of the 2nd polysilicon layer 15 in conjunction with the 1st polysilicon layer 13 forms a T-shaped polysilicon gate electrode, as shown in FIG. 1F. PA0 (9) Finally, as shown in FIG. 1G, taking advantage of the remaining 2nd polysilicon layer 15 as a mask, a reactive ion etching of the TEOS-oxide layer 14 is then performed to expose the Si substrate 11 area before salicide process, which is another important process to lower the gate parasitic resistance. PA0 (1) Form a pad oxide layer and a silicon nitride layer in form of a gate shape on the P-type Si substrate. PA0 (2) A self-aligned ion implanting process is applied to form lightly-doped-drain areas. PA0 (3) Form a BPSG (Boron PhosphoSilicate Glass) layer and planarize the surface. PA0 (4) Etch back the BPSG layer to expose the silicon nitride surface, and remove the Silicon Nitride layer and the pad oxide layer. PA0 (5) Form a gate oxide layer in the active gate area and a 1st polysilicon layer on the entire wafer, and planarize the surface such that the respective surfaces of BPSG layer and the 1st polysilicon layer poses at the same level. PA0 (6) Form 2nd polysilicon layer by a selective CVD technique, and thereby to achieve a T-shaped gate electrode. PA0 (7) Another self-aligned ion implanting process is applied to form heavily-doped source and drain areas.
However, in the aforementioned T-shaped gate processes, after the formation of the gate oxide layer 12, reactive ion etching steps are still required, and would cause serious plasma charging damage to the gate oxide. As the reactive ion etching is performed, some positive charges accumulate in the polysilicon layer, and some negative charges accumulate in the blocking capacitor of the reactor. As long as the etching is finished and the power is turned off, those positive and negative charges will gather on either side of the gate oxide layer, and a sufficient voltage may develop across the gate oxide to result in dielectric breakdown. In this case, the yield rate of the process will drop. There are other alternatives to achieve the T-shaped gate electrode, which demand several more photolithographic steps and are not cost effective.